module cla16(A,B,Cin,S,Cout,zero);

    input   [15:0]  A,B;
    input           Cin;
    output  [15:0]  S;
    output          Cout;
    output          zero;

    wire            c0,c4,c8,c12,c16;
    wire            p0,p4,p8,p12;
    wire            g0,g4,g8,g12;
    wire            s0,s4,s8,s12;

    assign  c0 = Cin;
    assign  c4 = g0 | p0&c0;
    assign  c8 = g4 | p4&c4;
    assign  c12 = g8 | p8&c8;
    assign  c16 = g12 | p12&c12;

    cla4    U[3:0]  (
            .A(A),
            .B(B),
            .Cin({c12,c8,c4,c0}),
            .S(S),
            .pg({p12,p8,p4,p0}),
            .gg({g12,g8,g4,g0})
            );
    assign  Cout = c16;
    assign  zero = ~(| S);

endmodule
